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19-1785; Rev 1; 3/01
Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package
General Description
The MAX5360/MAX5361/MAX5362 are low-cost, 6-bit digital-to-analog converters (DACs) in miniature 5-pin SOT23 packages with a simple 2-wire serial interface that allows communication with multiple devices. The MAX5360 has an internal +2V reference and operates from a +2.7V to +3.6V supply. The MAX5361 has an internal +4V reference and operates from a +4.5V to +5.5V supply. The MAX5362 operates over the full +2.7V to +5.5V supply range and has an internal reference equal to 0.9 VDD. The fast-mode I2CTM-compatible serial interface allows communication at data rates up to 400kbps, minimizing board space and reducing interconnect complexity in many applications. Each device is available with one of four factory-preset addresses (see Selector Guide). The MAX5360/MAX5361/MAX5362 also include an output buffer, a low-power shutdown mode, and a poweron reset that ensures the DAC outputs are at zero when power is initially applied. In shutdown mode, the supply current is reduced to less than 1A and the output is pulled down with a 10k resistor to GND. The MAX5360/MAX5361/MAX5362 are available in miniature 5-pin SOT23 packages.
Features
o 6-Bit Accuracy in a Tiny 5-Pin SOT23 Package o Wide +2.7V to +5.5V Supply Range (MAX5362) o 1A Shutdown Mode o Buffered Output Drives Resistive Loads o Low Glitch Power-On-Reset to Zero DAC Output o Fast I2C-Compatible Serial Interface o -5% Full-Scale Error (MAX5362) o 1LSB (max) INL/DNL o Low 230A max Supply Current
MAX5360/MAX5361/MAX5362
Ordering Information
PART MAX5360_EUK-T* MAX5361_EUK-T* MAX5362_EUK-T* TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 5 SOT23-5 5 SOT23-5 5 SOT23-5
*See Selector Guide for address options.
Selector Guide
PART MAX5360LEUK MAX5360MEUK MAX5360NEUK MAX5360PEUK MAX5361LEUK MAX5361MEUK MAX5361NEUK MAX5361PEUK MAX5362LEUK MAX5362MEUK MAX5362NEUK MAX5362PEUK ADDRESS 0x60 0x62 0x64 0x66 0x60 0x62 0x64 0x66 0x60 0x62 0x64 0x66 REFERENCE +2.0V +2.0V +2.0V +2.0V +4.0V +4.0V +4.0V +4.0V 0.9 VDD 0.9 VDD 0.9 VDD 0.9 VDD TOP MARK ADMM ADMY ADNE ADMO ADMU ADNA ADNG ADMQ ADMW ADNC ADNI ADMS
Applications
Automatic Tuning (VCO) Power Amplifier Bias Control Programmable Threshold Levels Automatic Gain Control Automatic Offset Adjustment
I2C is a trademark of Philips Corp.
Typical Operating Circuit
+2.7V TO +5.5V
Pin Configuration
TOP VIEW
OUT 1 VDD SDA SCL 5 SCL
VDD C PX.0/SDA PX.1/SCL GND
MAX5362
GND
OUT
GND 2
MAX5360 MAX5361 MAX5362
4 SDA
VDD 3
SOT23-5
________________________________________________________________ Maxim Integrated Products
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Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package MAX5360/MAX5361/MAX5362
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V OUT to GND ...............................................-0.3V to (VDD + 0.3V) SCL, SDA to GND.....................................................-0.3V to +6V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 5-Pin SOT23 (derate 7.1mW/C above +70C)...........571mW Operating Temperature Range MAX536__EUK-T ............................................-40C to +85C Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 3.6V (MAX5360); VDD = 4.5V to 5.5V (MAX5361); VDD = 2.7V to 5.5V (MAX5362); RL =10k, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25C.) PARAMETER STATIC ACCURACY Resolution Integral Linearity Error Differential Linearity Error Offset Error Offset Error Supply Rejection Offset Error Temperature Coefficient Full-Scale Error Full-Scale Error Supply Rejection Full-Scale Error Temperature Coefficient DAC OUTPUT MAX5360 Internal Reference (Note 5) REF MAX5361 MAX5362 Output Load Regulation Output Resistance DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Digital Feedthrough Digital-Analog Glitch Impulse Wake-Up Time Code = 63, 0 to 100A Code = 0, 0 to -100A VOUT = 0 to VDD, power-down mode Positive and negative To 1/2LSB, 50k and 50pF load (Note 6) Code = 0, all digital inputs from 0 to VDD Code 31 to 32 From software shutdown 1.8 3.6 0.85 VDD 2 4 0.9 VDD 0.5 0.5 10 0.4 20 2 40 50 2.2 4.4 0.95 VDD V INL DNL VOS (Note 1) Guaranteed monotonic (Note 2) Guaranteed monotonic (Note 2) MAX5362 (Notes 2, 3) (Note 2) Code = 63 MAX5360/MAX5361 MAX5362 MAX5360/MAX5361 MAX5362 MAX5360/MAX5361 MAX5362 40 10 60 3 1 10 5 60 1 6 1 1 2 Bits LSB LSB mV dB ppm/C % of Ideal FS dB ppm/C SYMBOL CONDITIONS MIN TYP MAX UNITS
Code = 63, MAX5360/MAX5361 (Note 4) Code = 63
LSB k V/s s nVs nVs s
2
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Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX5360); VDD = 4.5V to 5.5V (MAX5361); VDD = 2.7V to 5.5V (MAX5362); RL =10k, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25C.) PARAMETER POWER REQUIREMENTS MAX5360 Supply Voltage VDD MAX5361 MAX5362 Supply Current DIGITAL INPUTS (SCL, SDA) Input Low Voltage Input High Voltage Input Hysteresis Input Capacitance Input Leakage Current Pulse Width of Spike Suppressed DIGITAL OUTPUT (SDA) (open drain) Output Low Voltage VOL ISINK = 3mA ISINK = 6mA VIH min to VIL max, bus capacitance 10pF to 400pF ISINK = 3mA ISINK = 6mA 0 0 0.4 0.6 250 ns 250 V VIL VIH Vhys CIN Ii tSP 0 (Note 7) 0.7 VDD 0.05 VDD 10 10 50 0.3 VDD V V V pF A ns IDD No load, all digital inputs at 0 or VDD, code = 63 Shutdown mode 2.7 4.5 2.7 150 3.6 5.5 5.5 230 1 A V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5360/MAX5361/MAX5362
Output Fall Time
tof
TIMING CHARACTERISTICS
(VDD = 2.7V to 3.6V (MAX5360); VDD = 4.5V to 5.5V (MAX5361); VDD = 2.7V to 5.5V (MAX5362); RL =10k, CL = 50pF, TA = TMAX to TMIN, Figure 3, unless otherwise noted. Typical values are TA = +25C.) PARAMETER SCL Clock Frequency Bus-Free Time Between a STOP and a START Condition Hold Time (Repeated) START Condition Low Period of the SCL Clock High Period of the SCL Clock SYMBOL fSCL tBUF tHD, STA tLOW tHIGH CONDITIONS MIN 0 1.3 0.6 1.3 0.6 TYP MAX 400 UNITS kHz s s s s
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Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package MAX5360/MAX5361/MAX5362
TIMING CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX5360); VDD = 4.5V to 5.5V (MAX5361); VDD = 2.7V to 5.5V (MAX5362); RL =10k, CL = 50pF, TA = TMAX to TMIN, Figure 3, unless otherwise noted. Typical values are TA = +25C.) PARAMETER Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals Setup Time for STOP Condition Capacitive Load for Each Bus Line Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: SYMBOL tSU, STA tHD, DAT tSU, DAT tr tf tSU, STO Cb 0.6 400 CONDITIONS MIN 0.6 0 100 300 300 0.9 TYP MAX UNITS s s ns ns ns s pF
Guaranteed from code 1 to code 63. The offset value extrapolated from the range over which the INL is guaranteed. MAX5362, tested at VDD = 5V 10%. MAX5360, tested at VDD = 3V 10%; MAX5361, tested at VDD = 5V 10%. Actual output voltage at full scale is 63/64 VREF. Output settling time is measured by taking the code from code 1 to code 63, and from code 63 to code 1. Guaranteed by design.
Typical Operating Characteristics
(VDD = 3V (MAX5360), VDD = 5V (MAX5361/MAX5362), TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. TEMPERATURE
MAX5360/1/2-02 MAX5360/1/2-03
INTEGRAL NONLINEARITY vs. CODE
0.030 0.025 0.020 0.015 0.010 0.005 0 -0.005 -0.010 -0.015 -0.020 -0.025 -0.030 -0.035 -0.040 -0.045 0 25 CODE 50
MAX5360/1/2-01
INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE
0
0
INL (LSB)
INL (LSB)
INL (LSB)
-0.025
-0.025
-0.050 75 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
-0.050 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
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Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package
Typical Operating Characteristics (continued)
(VDD = 3V (MAX5360), VDD = 5V (MAX5361/MAX5362), TA = +25C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE
MAX5360/1/2-04 MAX5360/1/2-05
MAX5360/MAX5361/MAX5362
DIFFERENTIAL NONLINEARITY vs. CODE
0 -0.005 0.010 0.005 DNL (LSB) 0 -0.005 -0.010 -0.015 -0.020 0 25 CODE 50 75 -0.020
DIFFERENTIAL NONLINEARITY vs. TEMPERATURE
MAX5360/1/2-06
0 -0.005
DNL (LSB)
-0.015
DNL (LSB) 2.5 3.0 3.5 4.0 4.5 5.0 5.5
-0.010
-0.010
-0.015
-0.020
-0.025 SUPPLY VOLTAGE (V)
-0.025 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
TOTAL UNADJUSTED ERROR vs. CODE
MAX5360/1/2-07
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX5360/1/2-08
OFFSET ERROR vs. TEMPERATURE
MAX5360/1/2-09
0.15 0.10 0.05 TUE (LSB)
0
0
-0.25
VOS 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0 -0.05 -0.10 -0.15 -0.20 0 25 CODE 50 75
VOS (mV)
-0.25
-0.50 SUPPLY VOLTAGE (V)
-0.50 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
FULL-SCALE ERROR vs. TEMPERATURE
0.75 0.50 FULL-SCALE ERROR (LSB) 0.25 0 -0.25 -0.50 NO LOAD -0.75 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) -1.2 -0.75
MAX5360/1/2-10
FULL-SCALE ERROR vs. TEMPERATURE
1.2 0.8 FULL-SCALE ERROR (LSB) FULL-SCALE ERROR (%) 0.4 0 -0.4 -0.8 0.75 0.50 0.25 0 MAX5362 -0.25 -0.50 -0.4 -0.8 -1.2 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) MAX5360 MAX5361
MAX5360/1/2-11
SUPPLY CURRENT vs. SUPPLY VOLTAGE
180
MAX5360/1/2-12
MAX5361 MAX5360 MAX5362
1.2 0.8 FULL-SCALE ERROR (%) SUPPLY CURRENT (A) 0.4 0
200 MAX5361 MAX5360
160 140 120 100 80 60 40 20 0 2.5
MAX5362
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
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Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package MAX5360/MAX5361/MAX5362
Typical Operating Characteristics (continued)
(VDD = 3V (MAX5360), VDD = 5V (MAX5361/MAX5362), TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX5360/1/2-13
SUPPLY CURRENT vs. CODE
MAX5360/1/2-14
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5360/1/2-15
160 155 SUPPLY CURRENT (A) 150 145 140 135 130 -40 -20 0 20 40 60 80 MAX5361
160 155 SUPPLY CURRENT (A) 150 145 140 135 130 MAX5361 VDD = 5V MAX5362 VDD = 5V
1.0 08 SUPPLY CURRENT (A)
0.6
MAX5362 MAX5360
0.4
MAX5360 VDD = 5V
MAX5360 VDD = 3V
0.2
0 0 8 16 24 32 CODE 40 48 56 64 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
100
TEMPERATURE (C)
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
MAX5360/1/2-16
OUTPUT LOAD REGULATION
4.5 VOUT FULL SCALE (V) 4.0 3.5 3.0 2.5 2.0 1.5 C D E 0.1 0 B 0.2 VOUT ZERO CODE (V) VDD 2V/div OUT 50mV/div A
MAX5360/1/2-17
OUTPUT VOLTAGE ON POWER-UP
MAX5360/1/2-18
1.0 0.8 SUPPLY CURRENT (A)
0.6 VDD = 5V 0.4 VDD = 3V 0.2
0 -40 -20 0 20 40 60 80 100 0 1 2 3 4 5 6 7 8 9 10 TEMPERATURE (C) LOAD CURRENT (mA)
4s/div
A: MAX5361/MAX5362, VDD = 4.5V, FULL-SCALE OR SOURCING B: MAX5360, FULL-SCALE, VDD = 2.7V SINKING, VDD = 5V SOURCING C: MAX5360, FULL-SCALE, VDD = 2.7V, SOURCING D: ZERO CODE, VDD = 2.7V, SINKING E: ZERO CODE, VDD = 5.5V SINKING
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Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package
Typical Operating Characteristics (continued)
(VDD = 3V (MAX5360), VDD = 5V (MAX5361/MAX5362), TA = +25C, unless otherwise noted.)
MAX5360 OUTPUT VOLTAGE EXITING SHUTDOWN
MAX5360/1/2-19
MAX5360/MAX5361/MAX5362
MAX5360 OUTPUT VOLTAGE ENTERING SHUTDOWN
MAX5360/1/2-20
MAX5360 OUTPUT SETTLING FROM 1/4 FS TO 3/4 FS
MAX5360/1/2-21
OUT 500mV/div
OUT 500mV/div
OUT 0.5V/div
SDA 3V/div
SDA 3V/div
SDA 3V/div
10s/div
1s/div
1s/div
MAX5360 OUTPUT SETTLING FROM 3/4 FS TO 1/4 FS
MAX5360/1/2-22
MAX5360 OUTPUT SETTLING 1/4LSB STEP-UP
MAX5360/1/2-23
MAX5360 OUTPUT SETTLING 1/4LSB STEP-DOWN
MAX5360/1/2-24
OUT 0.5V/div
OUT 20mV/div AC-COUPLED
OUT 20mV/div AC-COUPLED
SDA 3V/div
SDA 3V/div
SDA 3V/div
1s/div
2s/div 0 x 7F TO 0 x 80 01111111 TO 10000000
2s/div 0 x 80 TO 0 x 7F 10000000 TO 01111111
Pin Description
PIN 1 2 3 4 5 NAME OUT GND VDD SDA SCL DAC Voltage Output Ground Power-Supply Input Serial Data Input Serial Clock Input FUNCTION
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Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package MAX5360/MAX5361/MAX5362
VDD
VREF
REF CURRENTSTEERING DAC 255 SDA SCL CONTROL LOGIC DATA LATCH 6+2 SERIAL INPUT REGISTER MAX5360 MAX5361 MAX5362 OUT
SW1
SW2
SW255
10k
OUT
GND
Figure 1. Functional Diagram
Figure 2. Current-Steering Topology
Table 1. Unipolar Code Current
DAC CODE 6 BITS + 2 SUBBITS 111111 (00) 100000 (00) 000001 (00) 000000 (00) OUTPUT VOLTAGE MAX5360 2V (63/64) 1V 31mV 0 MAX5361 4V (63/64) 2V 62mV 0 MAX5362 0.9 VDD (63/64) 0.9 VDD / 2 0.9 VDD / 64 0
Detailed Description
The MAX5360/MAX5361/MAX5362 voltage-output, 6-bit DACs offer full 6-bit performance with less than 1LSB integral nonlinearity (INL) error and less than 1LSB differential nonlinearity (DNL) error ensuring monotonic performance. The devices use a simple two-wire, fastmode I2C-compatible serial interface that operates up to 400kHz. The MAX5360/MAX5361/MAX5362 include an internal reference, an output buffer, and low-current shutdown mode, making them ideal for low-power, highly integrated applications. Figure 1 shows the devices' functional diagram.
current is then converted to a voltage across a resistor, and this voltage is buffered by the output buffer amplifier. Output Voltage Table 1 shows the relationship between the DAC code and the analog output voltage. The 6-bit DAC code is binary unipolar with 1LSB = (VREF / 64). The MAX5360/ MAX5361 have a full-scale output voltage of (+2V 1LSB) and (+4V - 1LSB), respectively, set by the internal references. The MAX5362 has a full-scale output voltage of (0.9 VDD - 1LSB). Each device accepts 8-bit DAC codes, but the accuracy is guaranteed only for 6 bits. Output Buffer The DAC voltage output is an internally buffered unitygain follower that typically slews at 0.4V/s. The output can swing from 0 to full scale. With a 1/4 FS to 3/4 FS output transition, the amplifier outputs typically settle to 1/2LSB in less than 5s when loaded with 10k in parallel with 50pF. The buffer amplifiers are stable with any combination of resistive loads >10k and capacitive loads <50pF.
Analog Section
The MAX5360/MAX5361/MAX5362 employ a currentsteering DAC topology as shown in Figure 2. At the core of the DAC is a reference voltage-to-current converter (V/I) that generates a reference current. This current is mirrored to 255 equally weighted current sources. DAC switches control the outputs of these current mirrors, so only the desired fraction of the total current-mirror currents is steered to the DAC output. The
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Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package MAX5360/MAX5361/MAX5362
SDA tSU, DAT tLOW SCL tHD, STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD, DAT tSU, STA tHD, STA tSU, STO tBUF
Figure 3. Two-Wire Serial Interface Timing Diagram
VDD C SDA SCL SCL R S* VDD
MAX5360M 2V REFERENCE SDA OUT
Shutdown Mode The MAX5360/MAX5361/MAX5362 include a softwarecontrolled shutdown mode that reduces the supply current to <1A. All internal circuitry is disabled and an internal 10k resistor is placed from OUT to GND to ensure 0V at OUT while in shutdown. The device enters shutdown in less than 5s and exits shutdown in less than 50s.
OFFSET ADJUSTMENT
Digital Section
SCL VDD
MAX5361N 4V REFERENCE SDA OUT
THRESHOLD ADJUSTMENT
SCL
VDD
MAX5362P VDD REFERENCE SDA OUT RS* IS OPTIONAL.
GAIN ADJUSTMENT
Figure 4. Typical Application Circuit
Power-On Reset The MAX5360/MAX5361/MAX5362 have a power-on reset circuit to set the DAC's output to 0 when VDD is first applied or when VDD dips below 1.7V. This ensures that unwanted DAC output voltages will not occur immediately following a system startup, such as after a loss of power. The output glitch on startup is typically <50mV.
Serial interface The MAX5360/MAX5361/MAX5362 use a simple twowire serial interface requiring only two I/O lines (twowire bus) of a standard microprocessor (P) port. Figure 3 shows the timing diagram for signals on the 2wire bus. The two bus lines (SDA and SCL) must be high when the bus is not in use. The MAX5360/MAX5361/ MAX5362 are receive-only devices (slaves) and must be controlled by a bus master device. Figure 4 shows a typical application where multiple devices can be connected to the bus provided they have different address settings. External pullup resistors are not necessary on these lines (when driven by push-pull drivers), though the MAX5360/MAX5361/MAX5362 can be used in applications where pullup resistors are required (such as in I2C systems) to maintain compatibility with existing circuitry. The serial interface operates at SCL rates up to 400kHz. The SDA state is allowed to change only while SCL is low, with the exception of START and STOP conditions as shown in Figure 5. Each transmission consists of a START condition sent by the bus master device, followed by the MAX5360/MAX5361/ MAX5362's preset slave address, a power-mode bit,
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Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package MAX5360/MAX5361/MAX5362
Slave Address The MAX5360/MAX5361/MAX5362 are available with one of four preset slave addresses. Each address option is identified by the suffix L, M, N, or P added to the part number. The address is defined as the 7 most significant bits (MSBs) sent by the master after a START condition. The address options are 0x60, 0x62, 0x64, and 0x66 (left justified with LSB set to 0). The 8th bit, typically used to define a write or read protocol, sets the device's power mode (SHDN); the device is powered down when SHDN is set to 1. During a device search routine, the MAX5360/MAX5361/MAX5362 acknowledge both options (SHDN = 0 or SHDN = 1) but does not change its power state if a stop condition (or restart) is issued immediately. The second byte (DAC data) must be sent/received for the device to update both power mode and DAC output. DAC Data The 6-bit DAC data is decoded as straight binary MSB first with 1LSB = (VREF / 64) and converted into the corresponding analog voltage as shown in Table 1. Two subbits complete the data byte; these 2 bits should be set to zero since they are not tested to guaranteedmonotonic performance. After receiving the data byte, the MAX5360/MAX5361/ MAX5362 acknowledge its receipt and expect a STOP condition, at which point the DAC output is updated. The devices update the output and the power mode only if the second byte is clocked in (SHDN = 0) or out (SHDN = 1) of the device. When SHDN = 1, the master will read all ones when clocking out a data byte. The MAX5360/MAX5361/MAX5362 do not drive SDA except for the acknowledge bit.
SDA
SCL START CONDITION STOP CONDITION
Figure 5. Start and Stop Conditions
the DAC data (6 bits + 2 subbits), and finally, a STOP condition (Figure 6). The bus is then free for another transmission. SDA's state is sampled, and therefore must remain stable while SCL is high. Data is transmitted in 8-bit bytes. Nine clock cycles are required to transfer each byte to the MAX5360/MAX5361/MAX5362. Release SDA during the 9th clock cycle as the selected device acknowledges the receipt of the byte, by pulling SDA low during this time. A series resistor on the SDA line may be needed if the master's output is forced high while the selected device acknowledges (Figure 4).
SLAVE ADDRESS BYTE SDA 0 MSB SCL START CONDITION 1 2 3 4 5 6 1 1 0 0 X X LSB 7 8 9 SHDN ACK D6 MSB 10 11 12 D4 D3
DAC CODE D2 D1 D0 S1 S0 LSB 13 14 15 16 17 18 STOP CONDITION ACK
Figure 6. Complete Serial Transmission
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Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package MAX5360/MAX5361/MAX5362
VDD
C SDA SCL
typical I2C application. The communication protocol supports the standard I2C 8-bit communications. The general call address is ignored, and CBUS formats are not supported. The MAX5360/MAX5361/MAX5362 address is compatible with the 7-bit I2C addressing protocol only. No 10-bit formats are supported. RESTART protocol is supported, but an immediate STOP condition is necessary to update the DAC.
SCL
VDD
Applications Information
Digital Inputs and Interface Logic
OFFSET ADJUSTMENT
MAX5360L 2V REFERENCE SDA OUT
SCL
VDD
MAX5361M 4V REFERENCE OUT SDA
THRESHOLD ADJUSTMENT
The serial 2-wire interface has logic levels defined as VOL = 0.3 VDD and VOH = 0.7 VDD. All of the inputs include Schmitt-trigger buffers to accept slow-transition interfaces. This means that optocouplers can interface directly to the MAX5360/MAX5361/MAX5362 without additional external logic. The digital inputs are compatible with CMOS logic levels and must not be driven with voltages higher than VDD.
Power-Supply Bypassing and Layout
SCL VDD MAX5362P VDD REFERENCE OUT SDA
GAIN ADJUSTMENT
Figure 7. I2C Typical Application
Careful PC board layout is important for best system performance. To reduce crosstalk and noise injection, keep analog and digital signals separate. Ensure that the ground return from GND to the supply ground is short and low impedance; a ground plane is recommended. Bypass VDD with a 0.1F to ground as close as possible to the device. If the supply is excessively noisy, connect a 10 resistor in series with the supply and VDD, and add additional capacitance
I 2C Compatibility The MAX5360/MAX5361/MAX5362 are compatible with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open drain that pulls the data line low during the 9th clock pulse. Figure 7 shows a
Chip Information
TRANSISTOR COUNT: 2910 PROCESS: BiCMOS
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Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package MAX5360/MAX5361/MAX5362
Package Information
SOT5L.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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